p-mean Model impact on VLSI Placement
نویسنده
چکیده
In this paper we compare the impact of of p-mean Half-perimeter wirelength (HPWL) model on analytical placement of VLSI. against logarithm-sum-expontial (LSE) wirelength model, weighted average(WA) [3]and (γ,p)[8] wirelength models.. Deployment of the wirelength model in analytical placement engine produces 12%, 10% and 1% shorter wirelength than widely used LSE and recently proposed weighted average(WA) [3]and (γ,p)[8] wirelength models. KeywordsVLSI; placement; wirelength; simulated annealing ________________________________________________________________________________________________________
منابع مشابه
Discrete Multi Objective Particle Swarm Optimization Algorithm for FPGA Placement (RESEARCH NOTE)
Placement process is one of the vital stages in physical design. In this stage, modules and elements of circuit are placed in distinct locations according to optimization basis. So that, each placement process tries to influence on one or more optimization factor. In the other hand, it can be told unequivocally that FPGA is one of the most important and applicable devices in our electronic worl...
متن کاملT3: Physical Design
Description: The objective of the tutorial is to survey recent algorithms and methodologies that have had (or are likely to have) a significant impact on the physical design industry. A second objective is to provide industrial feedback to the academic community in an effort to increase the relevance of academic research to industrial needs. Outline: Data Structures for VLSI, Partitioning, Floo...
متن کاملSpice Compatible Model for Multiple Coupled Nonuniform Transmission Lines Application in Transient Analysis of VLSI Circuits
An SPICE compatible model for multiple coupled nonuniform lossless transmission lines (TL's) is presented. The method of the modeling is based on the steplines approximation of the nonuniform TLs and quasi-TEM assumptions. Using steplines approximation the system of coupled nonuniform TLs is subdivided into arbitrary large number of coupled uniform lines (steplines) with different characteristi...
متن کاملDeterministic and Probabilistic Models on Vlsi Cell Placement-a Survey
General VLSI Cell placement has gone through different versions depending upon the particular applications. The area under modern challenges of VLSI desgin throw light on Power minimization, Thermal capacity and Area occupation. Thus Utility function, Renewal reward and Hypergraph setup are utilized in our discussion. A brief review is given in this paper . .
متن کاملAn Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques
In recent years, size of VLSI circuits is dramatically grown and layout generation of current circuits has become a dominant task in design flow. Standard cell placement is an effective stage of physical design and quality of placement affects directly on the performance, power consumption and signal immunity of design. Placement can be performed analytically or heuristically. Analytical placer...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2015